Speeding up is always one of the attempts in the ROM design. For a high-speed memory, the main bottleneck in design is the low speed on the word line owing to the large resistance and parasitic capacitance inherent in a polysilicon word line, and there have been proposed two solutions for improving thereto. The first one is to separate a word line into several segments along the length thereof, and provide for each segment of the word line with an individual word line driver, so as to have a higher operating speed of the memory. In other words, the memory is separated into several small ones in this solution. For more illustrative, FIG. 1 is a schematic diagram of this solution, in which FIG. 1A is a simplified diagram of showing several word lines 10 and word line drivers 12 for driving the word lines 10 in a memory before the word line 10 is separated into multiple segments, and FIG. 1B is a simplified diagram of showing each of the word lines 10 in FIG. 1A having been separated into two segments 102 and 104. In FIG. 1A, each word line 10 has a length of L, and each word line 10 is driven by a word line driver 12. After separated into two segments 102 and 104 along the length L, each word line 10 is provided with two drivers 12 for the segments 102 and 104, respectively. For each segment 102 or 104 of a word line 10, the resistance and parasitic capacitance thereof are only half as large as that of the original one, and therefore the operating speed thereto is improved. However, this solution requires a large number of additional word line drivers 12, thereby dramatically increasing the circuit area of the memory.
The other solution for speeding up a memory is to connect a word line with a metal line in parallel along the direction of the word line to reduce the RC delay thereof, and this metal line is referred to as a word line strap. The word line strap technique will not requests much more additional layout area, but is only available for those processes of two or more metal layers, due to the requirement of looser contacts in an array for the contacts to be slightly shifted in their locations so as to insert local metal word lines in the direction along the bit lines of the memory to connect the respective word lines in each memory banks. For more illustrative to the use of the word line strap, FIG. 2 shows a schematic diagram of a simplified memory 20, in which each of two memory banks Bank0 and Bank1 includes a word line WL0, and each of the word lines WL0 is connected with a word line strap 204 or 206 in parallel by its side to reduce the resistance thereof. In the memory 20, the bit lines BL0 and BL1, virtual ground lines VG0 and VG1, and local word line LWL0 are formed from a first metal layer and perpendicular to the word lines WL0 in the banks Bank0 and Bank1, and the word line straps 204 and 206, and global word line GWL0 are formed from a second metal layer, in which the local word line LWL0 connects the word line straps 204 and 206 to the global word line GWL0 through contacts 208, 210, and 212, respectively, and the dash line 202 indicates the word line signal path.
FIG. 3 provides a circuit diagram of a conventional flat cell ROM to show why the word line strap technique is not available for flat cell ROMs. In a memory 30, a memory array 32 includes several transistors 322 serving as memory cells arranged in a manner that the gates of the transistors 322 on the same row are connected to a common word line among WL0-WLN, and the sources/drains of the transistors 322 on the same column are connected to a common bit line BL or virtual ground line VG, and select lines SL0 and SL1 to select the bit line BL and virtual ground line VG. FIG. 4 shows a layout of the circuit 30 shown in FIG. 3, in which Bank0, Bank1, and Bank2 represent different memory banks. In the memory bank Bank1, each bit line BL and each virtual ground line VG are connected to a respective bit signal line 36 and a respective virtual ground signal line 38 through a respective contact 34. It is shown in FIG. 4 that there is no enough space between the adjacent contacts 34 allowed the contacts 34 to be slightly shifted in their locations and therefore, inserting any local word line between the bit signal line 36 and virtual ground signal line 38 will push the adjacent structures away from the original locations in the X-direction and enlarge the layout area.
Therefore, it is desired a flat cell ROM available for the word line strap technique to be applied without an enlarged layout area.